Statistics data is a key part of any data processing system. Due to faster data circuit rates, data processing is often distributed across multiple processing devices.
FIG. 1 is a block diagram of an exemplary data processing system. As illustrated in FIG. 1, the data processing system 100 includes a management plane, for example a central processing unit (CPU) 101 coupled to multiple processing devices (D1–D4) 102–105. Processing devices 102–105 process data and store statistics data S1–S4 in respective associated memory devices (not shown). The CPU 101 reads the memory associated with each processing device 102–105 and retrieves the corresponding statistics data S1–S4, sequentially or according to a priority mechanism, such as a round robin mechanism.
As the number of circuits and the amount of statistics data per circuit increase, the CPU 101 needs to collect statistics data at a higher frequency. However, fast collection of statistics data is hampered by the comparatively slower interfaces to the processing devices 102–105 and by the fact that the CPU 101 needs to poll each device in order to collect statistics data, irrespective of the availability of statistics data in that particular device, possibly resulting in bandwidth waste.